Referring to FIG. 1, a register access controller 100 of the prior art controls the transfer of data from a register page 102 to a bus interface 104. The register page 102 is comprised of a plurality of registers including a first register 111, a second register 112, a third register 113, and so on, up to a sixty-fourth register 164.
An example application which uses such a transfer of data from a register page to a bus interface is an Ethernet computer network peripheral device installed within a computer to interface that computer to a network of computers. In that example, the register page 102 with the register access controller 100 is part of the Ethernet computer network peripheral device. Also in that example, the bus interface 104 is a bus interface between the Ethernet computer network peripheral device and the CPU of the computer in which the Ethernet computer network peripheral device is installed.
In that example, each register in the register page 102 may include data packets and other types of data received by the Ethernet computer network peripheral device from the network of computers which may be the Internet. The CPU of the computer in which the Ethernet computer network peripheral device is installed reads the data from the registers within the register page 102 in a mode commonly termed "the slave mode" to further process the data within the register page 102.
The data from each of the registers of the register page 102 is transferred to the bus interface 104 on a register by register basis. Referring to FIG. 1, each register has a respective output driver coupled between that register and the bus interface 104. In FIG. 1, a first output driver 120 is coupled between the first register 111 and the bus interface 104, and so on, with a sixty-fourth output driver 122 being coupled between the sixty-fourth register 164 and the bus interface 104. (Note that the respective output driver corresponding to the other registers aside from the first register 111 and the sixty-fourth register 164 are not shown in FIG. 1 for clarity of illustration.)
Each output driver turns on to couple the respective register corresponding to that output driver to the bus interface 104 or turns off to decouple the respective register to the bus interface 104. A 6-bit address line 124 indicates a selected register of the 64 registers of the register page 102 for being coupled to the bus interface 104. An address decoder 126 decodes the data on the 6-bit address line 124 and generates a first control signal which turns on the respective output driver of the selected register. In FIG. 1, the first control signal may be a high output at an output line coupled to the respective output driver of the selected register and low outputs at output lines coupled to the respective output driver of the rest of the plurality of registers of the register page 102.
A memory unit of an Ethernet computer network peripheral device may be organized into a plurality of register pages. In that case, a register page select input 128 is included to indicate which register page of the plurality of register pages is currently being read. In FIG. 1, the register page select input 128 is in a high state if the register page 102 of FIG. 1 of the plurality of register pages is selected for data transfer to the bus interface 104. The register page select input 128 is in a low state if the register page 102 of FIG. 1 of the plurality of register pages is not selected for data transfer to the bus interface 104.
In FIG. 1, a respective AND gate is coupled to each output driver. A first AND gate 130 is coupled to the first output driver 120, and so on, with a sixty-fourth AND gate 132 being coupled the sixty-fourth output driver 122. A first input of each AND gate is coupled to the register page select input 128, and a second input of each AND gate is coupled to a respective output line of the address decoder 126. When the register page select input 128 is a low state, the register page 102 of FIG. 1 of the plurality of register pages is not selected for data transfer to the bus interface 104. Thus, the output of all AND gates are low and controls each output driver to turn off to decouple all registers of the register page 102 from the bust interface 104.
When the register page select input 128 is a high state, the register page 102 of FIG. 1 is selected for data transfer to the bus interface 104. In that case, the respective AND gate of a selected register has a high input from the address decoder. Then, that AND gate with a high output drives the respective output driver of that selected register to turn on to couple the selected register to the bus interface 104.
Assuming that the register page 102 of FIG. 1 has been selected for data transfer to the bus interface (i.e. the register page select input 128 is in a high state), data from the plurality of registers of the register page 102 is transferred to the bus interface 104 on a register by register basis. For speed optimized data transfer commonly called "zero-wait continuous burst data transfer", data from a different register is transferred to the bus interface 104 every clock period.
Referring to FIG. 2, a clock signal 202 includes a periodic transition at the beginning 204 of every period of the clock signal. A period of the clock signal is indicated by a time period 206. In zero-wait continuous burst data transfer, the 6-bit address line 124 changes to indicate a different selected register of the plurality of register 102 at every periodic transition of the clock signal. Thus, with zero-wait continuous burst data transfer, data is transferred from a different selected register during every period of the clock signal 202 maximizing the amount of data transferred from the register page 102 to the bus interface for a given amount of time.
Referring to FIGS. 1 and 2, assume that the first register 111 is the selected register during the first period 206 of the clock signal 202. A first control signal 208 for the first register 111 from the address decoder 126 goes high at the beginning of the first period 206 and goes low after the end of the first period 206. The first control signal 208 is an input to the first AND gate 130 and turns on the first output driver 120 during its high state.
Assume also that the sixty-fourth register 164 is the next selected register during a second period 210 of the clock signal 202. A second control signal 212 for the sixty-fourth register 164 from the address decoder 126 goes high at the beginning of the second period 210 and goes low after the end of the second period 210. The second control signal 212 is an input to the sixty-fourth AND gate 132 and turns on the sixty-fourth output driver 122 during its high state.
As illustrated in FIG. 2, if the delay in the first control signal 208 turning back low after the first period 206 is sufficient, then an overlap time 214 may exist where both the first control signal 208 and the second control signal 212 are high. In that case, both the first output driver 120 and the sixty-fourth output driver 122 may be turned on simultaneously during the overlap time 214. When both of those output drivers 122 and 124 are on, both the first register 111 and the sixty-fourth register 164 are coupled to the bus interface (i.e. those two registers 111 and 164 are shorted together). With such a short circuit, high current may flow through this short circuit between the first register 111, the first output driver 120, the sixty-fourth register 164, and/or the sixty-fourth output driver 122. This high current may lead to erratic circuit behavior and even permanent damage to the integrated circuit including the register page 102. Thus, it would be desirable to prevent simultaneous coupling of more than one register of the register page 102 to the bus interface 104.